1. Field of the Invention
The present invention relates to an output control circuit of a microcomputer, more particularly to, an output control circuit known as so-called programmable input/output port that allows switching functions of an output terminal of the microcomputer by means of software.
2. Description of the Related Art
FIG. 1 is a block diagram illustrating an example of conventional configuration arrangement wherein the input/output terminal serves as a function of an input/output port as well as a function of an output of PWM waveform for driving a three-phase motor, when a microcomputer is used as an actuator control apparatus.
in FIG. 1, numeral 30 denotes a microcomputer, and 100 an actuator, for example, a three-phase motor controlled by the microcomputer 30.
The actuator 100 is driven and controlled by means of a control signal outputted from an input/output terminal 5 of the microcomputer 30. The actuator 100 is equipped with a sensor 101 that generates a sensor signal rising from "L" level to "H" level when a certain state of the actuator 100 is detected, and inputs it through an external input terminal 32 of the microcomputer 30 to a CPU 31. Thus, the CPU 31 of the microcomputer 30 controls the actuator 100 according to the sensor signal of sensor 101 inputted through the external input terminal 32.
In FIG. 1, the CPU 31 and an output control circuit are shown as an internal configuration of the microcomputer 30.
Numeral 1 denotes a direction register to which data for specifying the input/output direction of a signal from the input/output terminal 5 is set, 2 a port latch for holding a data inputted/outputted into/from the input/output terminal 5, 3 a flip-flop for generating a PWM waveform, and 4 an operation mode register to which data for specifying whether the input/output terminal 5 should serve as an input/output terminal of the data or an output terminal for a PWM waveform is set, and all of them are connected with the CPU 31 by means of a data bus 6.
Numeral 51 denotes an OR gate receiving an output of the direction register 1 at one input terminal and an output of the operation mode register 4 at the other input terminal thereof. An output of the OR gate 51 is directly inputted to an input terminal of a NAND gate 57, inverted by an inverter 56, and further inputted, then, to an input terminal of a NOR gate 58.
Numerals 52 and 53 are gates controlled by data set in the operation mode register 4. The gate 52 conducts when the output of the operation mode register 4 is at "L" level (data "0" is set), and outputs the content of the port latch 2. An output of the gate 52 is inputted to the other input terminal of the NAND gate 57 and the other input terminal of the NOR gate 58. The gate 53 conducts when the output of the operation mode register 4 is at "H" level (data "1" is set), and outputs the content, of the flip-flop 3. An output of the gate 53 is connected with the output of the gate 52 in wired OR arrangement.
Accordingly, the gate 53 conducts when the output of the operation mode register 4 is at "H" level ("1"), and the output (PWM waveform) of the flip-flop 3 is inputted to the NAND gate 57 and NOR gate 58, while the gate 52 conducts when the output of the operation mode register 4 is at "L" level ("0"), and the content of the port, latch 2 is inputted to the NAND gate 57 and NOR gate 58.
Numerals 54 and 55 are gates controlled by data set in the direction register 1. The gate 54 conducts when the output of the direction register 1 is at "H" level (data "1" is set), and outputs the content of the port latch 2 to the data bus 6. The gate 55 conducts when the output of the direction register 1 is at "L" level (data "0" is set), and outputs a signal, which is inputted from the outside to the input/output terminal 5, to the data bus 6.
Thus, the gate 54 conducts when the output of the direction register 1 is at "H" level ("1"), and the content of the port latch 2 is outputted to the data bus 6, while the gate 55 conducts when the output, of the direction register 1 is at "L" level ("0"), and an input signal, which is inputted from the outside to the input/output terminal 5, is outputted to the data bus 6.
An output of the NAND gate 57 is supplied to a gate of a P-channel transistor 59. The P-channel transistor 59 is also connected with a source voltage at its source, the input/output terminal 5 and an input terminal of the gate 55 at its drain. On the other hand, an output of the NOR gate 58 is supplied to a gate of an N-channel transistor 60. The N-channel transistor 60 is also connected with the input/output terminal 5 and an input terminal of the gate 55 at its drain and a ground potential at its source.
When the input/output terminal 5 is used as a general input/output port, "0" is written into the operation mode register 4 by the CPU 31 through the data bus 6. Thereby, the gate 52 comes to be conductive state, and the gate 53 non-conductive state, data held by the port latch 2 is inputted to the other input terminals of the NAND gate 57 and NOR gate 58. In such state, when "0" is written into the direction register 1 by the CPU 31 through the data bus 6, as the output of the OR gate 51 is fixed to "0", that of the NAND gate 57 to "1", that of the NOR gate 58 to "0", and the gate 55 comes to be conductive state, an input signal, which is inputted from the outside to the input/output terminal 5, is supplied through the gate 55 to the port latch 2, and the value is stored.
On the other hand, when "1" is written in the direction register 1 through the data bus 6 by the CPU 31, the output of the OR gate 51 is fixed to "1", those of the NAND gate 57 and NOR gate 58 are inverted in value from that of the gate 52, and the gate 52 is conductive state, a value in the port latch 2 is outputted from the input/output terminal 5.
When the input/output terminal 5 is used as an output terminal of PWM waveforms, the CPU 31 writes "1" to the operation mode register 4 through the data bus 6. Accordingly, because the gate 52 comes to be non-conductive state, and the gate 53 conductive state, an output of the flip-flop 3 is inputted to the NAND gate 57 and NOR gate 58. In such a state, since the output of the OR gate 51 is fixed to "1" regardless of the content of direction register 1, a PWM waveform is outputted from the input/output terminal 5 as the CPU 31 periodically sets and resets the flip-flop 3 through the data bus 6. The actuator 100 can be, therefore, driven and controlled, when it is a three-phase motor or the like.
Thus, the output control circuit known as a programmable input/output port is provided with the direction register 1, operation mode register 4 and data bus 6, and can be programmed for allowing the input/output terminal 5 to serve as an input port or an output port by setting a value in the direction register 1 by means of the CPU 31 as well as for allowing the input/output terminal 5 to serve as an output terminal of PWM waveforms by setting a value in the operation mode register 4 by means of the CPU 31.
In a conventional output control circuit having such input/output terminal as described above as an input/output port and an output terminal of PWM waveforms, when a PWM waveform is outputted for driving a three-phase motor, the output of PWM waveform and port output must be controlled by switching to each other according to such external information, for example, as a rotating angle of the three-phase motor. However, at such switching operation, because the CPU must write data into the operation mode register by means of software as described above, it has been a problem that a time lag is caused, and a controlling accuracy is reduced.